This present invention relates to circuitry for protecting a circuit from destructive currents under reverse battery conditions.
Battery protection circuitry is typically provided to protect semiconductor circuits and systems from the damage that may occur when a battery is accidentally reversed or disconnected.
Integrated circuits (ICs) will typically be damaged when subjected to voltage and current having a polarity that is opposite to that for which they were designed. In order to protect ICs from reversed battery, a diode is commonly placed between the IC a the power supply terminals for the circuit. When a battery voltage having the correct polarity is coupled to the power supply terminals, then the protection diode is forward biased and allows the IC to receive the battery voltage and current. However, if the battery voltage is reversed, then the diode is reverse biased and the harmful voltage and current is prevented from reaching the IC. Also, the voltage drop introduced by the protection diode represents lost power and a reduced range of operating voltage because the input power supply must account for the threshold voltage drop.
The circuit and method of the present invention includes a battery protection circuit. The circuit and method of the present invention buffers a protected circuit from an input terminal that receives a power supply voltage.
An embodiment of a battery reversal protection circuit, according to the present invention, includes first and second input terminals for receiving a power supply voltage and an output terminal. A first transistor of the protection circuit has a control terminal and first and second current terminals, where the first current terminal of the first transistor is coupled to the first input terminal. A resistor is coupled between the control terminal of the first transistor and the second input terminal. A second transistor of the protection circuit has a control terminal and first and second current terminals. The control terminal of the second transistor is coupled to the first input terminal, the first current terminal of the second transistor is coupled to the output terminal, and the second current terminal of the second transistor is coupled to the control terminal of the first transistor. Further, a third transistor of the protection circuit has a control terminal, a bulk terminal, and first and second current terminals, where the third transistor is at least part of a protected circuit, the first current terminal of the third transistor being coupled to the first input terminal, the second current terminal of the third transistor being coupled to the output terminal, and the bulk terminal of the third transistor being coupled to the second current terminal of the first transistor.
An embodiment of a method, according to the present invention, for providing battery protection to a protected transistor, includes disposing the protected transistor between a first input terminal and an output terminal and receiving a power supply voltage at the first input terminal and a second input terminal. The method further calls for buffering a bulk terminal of the protected transistor from the first input terminal through a first transistor and driving a control terminal of the first transistor with a second transistor. The method further involves using the second transistor to detect when the power supply voltage at the first input terminal drops below an output voltage at the output terminal by a transistor threshold in order to prevent current flow between the first input terminal and the bulk terminal of the protected transistor. In a further refinement of the embodiment, the method further includes using a third transistor to sense when the supply voltage drops below an output voltage by a transistor threshold and to permit current to flow from the output terminal to a gate terminal of the protected transistor.
An embodiment of a low drop-out voltage regulator circuit with battery reversal protection, according to the present invention, includes first and second input terminals for receiving a power supply voltage and an output terminal for outputting a regulated voltage. The circuit also includes a voltage reference circuit having first and second supply terminals and an output terminal, where the second supply terminal of the voltage reference circuit is coupled to the second input terminal. An error amplifier is provided having first and second supply terminals, first and second input terminals, and an output terminal, where the second supply terminal of the error amplifier is coupled to the second input terminal, the first input terminal of the error amplifier is coupled to the output terminal of the voltage reference circuit, and the second input terminal of the error amplifier is coupled to the output terminal through a resistive divider. The circuit includes a power transistor having a control terminal, a bulk terminal, and first and second current terminals, where the control terminal of the power transistor is coupled to the output terminal of the error amplifier, and the second current terminal of the power transistor is coupled to the output terminal. A first transistor of the circuit has a control terminal and first and second current terminals. The first current terminal of the first transistor is coupled to the first input terminal and the second current terminal of the first transistor is coupled to the first supply terminal of the voltage reference circuit and the first supply terminal of the error amplifier. A resistor is coupled between the control terminal of the first transistor and the second input terminal. A second transistor of the circuit has a control terminal and first and second current terminals. The control terminal of the second transistor is coupled to the output terminal, the first current terminal of the second transistor is coupled to the output terminal, and the second current terminal of the second transistor is coupled to the control terminal of the first transistor. Finally, a third transistor of the circuit has a control terminal and first and second current terminals. The control terminal of the third transistor being coupled to the second current terminal of the second transistor, the first current terminal of the third transistor being coupled to the first input terminal, and the second current terminal of the third transistor being coupled to the bulk terminal of the power transistor.
Finally, a second transistor is provided having a control terminal and first and second current terminals. The control terminal of the second transistor is coupled to the output terminal, the first current terminal of the second transistor is coupled to the output terminal, and the second current terminal of the second transistor is coupled to the control terminal of the first transistor. In a further refinement of this embodiment, the power transistor further includes a bulk terminal and the circuit further includes a third transistor having a control terminal and first and second current terminals, the control terminal of the third transistor being coupled to the second current terminal of the second transistor, the first current terminal of the third transistor being coupled to the first input terminal, and the second current terminal of the third transistor being coupled to the bulk terminal of the power transistor.